In CRTs used for image display apparatuses, an electron beam strikes a phosphor surface to cause light emission. When measured for a miniscule period of time, each point of the screen is displayed only for an extremely short time by persistence of the phosphor. In CRTs, this point emission is sequentially scanned, to display an image of one frame using the persistence of vision by the eyes. This type of display device is called an impulse type display device.
In liquid crystal displays, a light modulation device generally called a hold type display device is used. In liquid crystal displays, display data is written in pixels arrayed in a matrix once for each frame using data lines (source lines) and address lines (gate lines). Each pixel holds the display data for the duration of one frame. That is, in liquid crystal displays, the screen is still being constantly displayed even when measured for a period of time smaller than one frame period.
In such a hold type image display apparatus, there occurs a visual phenomenon where the contour of a moving image is blurred. Taiichiro Kurita, “Picture Quality of Hold Type Display for Moving Images”, Technical Report of IEICE, EID99-10 (1999-06) reports why this phenomenon occurs and proposes methods for improving on this problem. From this report, it is found that the display quality of moving images can be greatly improved by shortening the display period in the frame time direction to a half or less of one frame.
An image display apparatus described in Japanese National Phase PCT Laid-Open Publication No. 08-500915 (hereinafter, simply called the conventional apparatus) is known as an image display apparatus capable of solving the above problem, in which the display period in the frame time direction is shortened to a half or less of one frame as proposed above to thereby provide a liquid crystal display with a feature close to the impulse type display. Hereinafter, this conventional apparatus will be described.
FIG. 14 illustrates a configuration of the conventional apparatus. The conventional apparatus includes a video signal time compression circuit 101, a PWM modulation pulse generation circuit 102, an inverter 103, a backlight 104, a liquid crystal (LCD) panel 105, an LCD controller 106, a source driver 107 and a gate driver 108. The LCD panel 105, the source driver 107, the gate driver 108, the LCD controller 106 and the backlight 104 are those used for general TFT liquid crystal displays, and therefore detailed descriptions of these components are omitted here.
FIG. 15 is a timing chart of the operation of the conventional apparatus. Hereinafter, referring to FIG. 15 as necessary, the operation of the conventional apparatus will be described. A video signal is inputted at the time at which the screen is sequentially scanned from the top to the bottom. In a signal timing scheme called VGA, the number of effective scanning lines is 480, the total number of scanning lines is 525, and the vertical synchronizing signal frequency is 60 Hz, in general. Under VGA, the time required from the input of the uppermost line of a screen until the input of the lowermost line of the screen is 480/525/60 [s]=15.2 [ms]. This time length is compressed with the video signal time compression circuit 101.
FIG. 16 illustrates a configuration of the video signal time compression circuit 101. The video signal time compression circuit 101 includes a dual port RAM 109, a write address control circuit 110, a read address control circuit 111 and a synchronizing signal control circuit 112. The dual port RAM 109 is a random access memory in which a write address/data port and a read address/data port are provided separately to enable independent write and read operations. An input video signal is inputted to the write port of the dual port RAM 109, and written in the dual port RAM 109 according to a write address outputted from the write address control circuit 110. The video signal data written in the dual port RAM 109 is read from the dual port RAM 109 according to a read address outputted from the read address control circuit 111, and outputted therefrom. The synchronizing signal control circuit 112, which receives an input vertical synchronizing signal, an input horizontal synchronizing signal and an input clock, controls the write address control circuit 110 and the read address control circuit 111, and outputs an output horizontal synchronizing signal and an output clock having frequencies increased from those of the inputs.
The operation of the video signal time compression circuit 101 of FIG. 16 will be described with reference to FIG. 17. The write address outputted from the write address control circuit 110 is counted with the input clock, and is reset with every input vertical synchronizing signal, i.e., every vertical blanking period. The data written to the dual port RAM 109 is the input video signal, each frame of which is stored in the dual port RAM 109. The output clock is generated by changing the input clock to a high-frequency clock by using a PLL synthesizer or the like. The read address is counted with the output clock, and is reset upon completion of read of data of each frame. The count of the read address is then stopped until it is restarted in synchronization with the reset timing of the count of the write address. By the operation described above, each frame of the input video signal is outputted in a time shorter than that required for the input.
The actual setting of the time required from the input of the uppermost line of a screen until the write of the lowermost line of the screen must be made in consideration of the write capabilities to liquid crystal pixels, such as the ON resistance of TFTs, the wiring resistance of gate lines and source lines, the pixel capacitance and the floating capacitance. The liquid crystal panel that permits the shortest TFT write time among those currently released as products is that of the UXGA resolution (1600 pixels horizontal×1200 pixels vertical). Since 1200/480 =2.5 considering the number of effective lines, the write time can be compressed by 1/2.5 for a panel of the VGA resolution. In other words, in this panel, the time required from the write of the uppermost line of a screen until the write of the lowermost line of the screen can be compressed from 15.2 ms to 6 ms.
In the liquid crystal panel 105, the liquid crystal is driven with data written in the respective TFT pixels. It is generally known that the response speed of liquid crystal is finite and low. In recent years, however, high-speed response liquid crystal such as optically self-compensated birefringence mode (OCB) liquid crystal has attracted attention. The OCB liquid crystal has exhibited a response time of about 4 ms (falling or rising time) in gray scale images, for example.
As shown in FIG. 15, for the display data written sequentially from the uppermost line of a screen, the liquid crystal starts responding sequentially from the uppermost line of the screen. Assume that the write time of one frame is 6 ms and the response time of liquid crystal (falling or rising time) is 4 ms, the time required from the write of the uppermost line of the screen until completion of the response of the lowermost line of the screen is 6+4=10 ms.
The PWM modulation pulse generation circuit 102 generates a modulation pulse having a width of 6.7 ms synchronizing with the vertical synchronizing signal. FIG. 18 shows the waveform of a lamp current for lighting up a cold-cathode tube as the light source of the backlight 104. The oscillating frequency of the inverter 103 is normally set at about 50 kHz in many cases. It is general practice to intermittently oscillate an inverter according to the waveform shown in FIG. 18, and this is called PWM modulation. In PWM modulation, the brightness of a lamp is controlled by changing the width of a modulation pulse for intermittent ON/OFF control of oscillation. The PWM modulation pulse generation circuit 102 generates the modulation pulse shown in FIG. 15 based on the vertical synchronizing signal. The inverter 103 controlled with this modulation pulse drives the backlight 104, to allow the backlight 104 to emit light for a duration of 6.7 ms. Thus, an image is displayed for only the duration of 6.7 ms in one frame period.
With the operation described above, the conventional apparatus overcomes the disadvantage of the liquid crystal device as a hold type display device, i.e., the phenomenon where the contour of a moving image is blurred.
However, in the conventional apparatus, flicker is generated because the backlight blinks at a frequency of 60 Hz in synchronization with the vertical synchronizing signal. This disadvantageously impairs the inherent advantage of liquid crystal displays that little flicker is generated and thus the viewer feels less fatigued when gazing at display details such as text characters.
The conventional apparatus has another problem in that the effect of improving on the blurring of a moving image decreases and the contour of a moving image is colored in the upper portion of the screen. Hereinafter, the causes of this decrease in the blurring improving effect and the coloring will be described.
In general, as for the phosphors for the cold-cathode tube fluorescent lamp used as the backlight 104, YOX is used as a read phosphor, LAP as a green phosphor, and BAM (or SCA) as a blue phosphor. FIG. 19 shows examples of persistent response characteristics of the respective phosphors. As seen from the figure, the persistence time of the green phosphor (LAP) is the longest, which is about 6.5 ms. The modulation pulse width shown in FIG. 15 can only be as great as 6.7 ms, considering the limitations of the currently achievable write capabilities to liquid crystal and the response time of liquid crystal as described above, whereas the persistence time of a currently typical fluorescent lamp is about 6.5 ms. This indicates that, during the time of about 6.5 ms shown by A in FIG. 15, the persistence of the backlight remains while an image signal for the next frame is written in the upper portion of the screen. Therefore, in a scene having motion, two frames may appear overlapping with each other, or the blurring of contours may not be improved in the upper portion of the screen. Moreover, the persistence times of the blue phosphor (BAM) and the red phosphor (YOX), which are about 0.1 ms and about 1.5 ms, respectively, are short compared with that of the green phosphor. Therefore, the overlap of two frames and the blurring of the contour in the upper portion of the screen described above occur only for green, and this results in coloring of the contour in green or magenta. The persistence time of the blue phosphor SCA is substantially the same as that of the blue phosphor BAM.
In view of the above, an object of the present invention is to provide an image display apparatus capable of improving on the problem of flicker while improving on motion blurring in a moving image. Another object of the present invention is to provide an image display apparatus capable of minimizing motion blurring and contour coloring that may occur on part of a screen while improving on motion blurring in a moving image.